1. Field of Invention
The present invention relates to a semiconductor device and the fabrication method thereof. More particularly, the present invention relates to a method for fabricating a memory device.
2. Description of Related Art
As the flash memories become more developed, they are customarily used in embedded application and sometimes in place of EPROM and EEPROM. The flash memory device allows multiple and repetitive writing, reading and erasure operations, and the storage data are retained even after the power supply is discontinued. Because of the aforementioned advantages, the flash memory has become the mainstream non-volatile memory device, which is widely applied in the electronic products, such as, personal computers, digital cameras and personal digital assistants (PDAs) etc.
At present, the commonly adopted flash memories can be classified as single gate flash memories, split gate flash memories and double gate flash memories. In general, the split gate flash memory cell (1.5T cell) is composed of a stacked gate consisting of a floating gate and a control gate, a select gate disposed on one side of the stacked gate and a source/drain region, while the double gate flash memory cell (2T cell) is composed of one stacked gate consisting of a floating gate and a control gate, source/drain regions and a select transistor disposed by one side of the stacked gate.
FIG. 1 is a top view illustrating a prior art memory structure. Referring to FIG. 1, a plurality of isolation structures 102 are disposed in the substrate 100. The isolation structures 102 define the active regions 104 in the substrate 100. The control gate line 114b, the floating gate (not shown), select gate line 115b and the source/drain region 116 constitute the first memory cell row 150, while control gate line 114a, the floating gate (not shown), select gate line 115a and the source/drain region 116 constitute the second memory cell row 160. Theoretically, the isolation structures 102 are formed as rectangle blocks in the design of the above flash memory structure. However, due to many uncontrollable factors of photolithography, corner rounding often occurs to the rectangle isolation structures 102 during the photolithography process. In order to solve the corner rounding problems, both ends of the isolation structure 102 are enlarged by the optical proximity correction technology. Therefore, the isolation structures 102 are customarily designed as a dumb-bell shape with both terminal blocks 102a enlarged. Because the enlarged ends of the isolation structures 102 occupy more areas in the active region 104 of the substrate 100, the prior art flash memory structure usually occupies more chip areas and hinders high integration of the device.
FIG. 2 is a cross-sectional view of the memory structure of FIG. 1. Referring to both FIGS. 1 and 2, after depositing the first polysilicon layer 108 for the floating gate, the first polysilicon layer is patterned to remove a portion of the first polysilicon layer above both the enlarged terminal blocks 102a of the isolation structures 102 and the locations predetermined for the control gate lines and, thus forming rectangle openings 103. From FIG. 2, the edges of the patterned first polysilicon layer 108 don not align with the edges of the isolation structures 102. Afterwards, the silicon oxide/silicon nitride/silicon oxide (ONO) layer 110 is formed covering the patterned first polysilicon layer 108 and the second polysilicon layer 112 is then deposited for forming the control gate lines and the select gate lines. However, the ONO layer and the polysilicon fence residue near the edge of the patterned first polysilicon layer 108 may result in horizontal two bits and cause reliability problems.
Moreover, once misalignment happens during defining the openings in the first polysilicon layer, the openings 103 may shift to undesirable positions, or even the predetermined location for the select gate line. In this case, the memory cells in different rows will have unequal electrical properties. In order to solve such problems, a predetermined distance is preserved between the corners of the expanded blocks of the isolation structures and the select gate line for keeping the select gate line away from the corners. Nonetheless, the distance between two adjacent memory cells is increased, leading to consuming more chip areas and preventing the device from having higher level of integration.